Conventional dynamic random access memories (DRAMs) perform data transfer operations in sequence. That is, when a read or write command is received and an address is made available, the data transfer operation, either read or write, is performed in its entirety before another command is accepted. Consequently, subsequent commands are delayed by the entire duration of the original data transfer.
The overall time to perform the original data transfer may be significant, because data transfers typically involve several steps, and each step takes time. For example, for a read operation, control logic of the DRAM must decode the command and address, perform precharge and equilibration, connect a row of memory cells to respective digit lines, allow time for sense amplifiers to develop signals, and transfer data from the sense amplifiers to an output data bus. Subsequent commands must wait until these operations are completed before they are accepted by the DRAM. Consequently, reading from and writing to the DRAM must be sufficiently slow to allow the original data transfer to be completed before a subsequent command is provided.
To reduce the amount of delay imposed in sequential data transfer operations, DRAMs can be "pipelined." In pipelining, each of the above-described steps is performed according to a specific timing sequence. For example, when the original data transfer operation progresses from a first step (e.g., command and address decode) to a second step (e.g., read data), a second data transfer progresses to its first step (command and address decode). Thus, the DRAM's control logic can begin decoding the second command and the DRAM's address decoder can begin decoding the second address while the data from the original data transfer operation is being read from or written to the memory array.
To control the flow of data through a pipelined DRAM, commands and data are transferred synchronously, and such DRAMs are referred to as synchronous DRAMs ("SDRAMs") . In SDRAMs, timing of operations is established relative to the leading edges of a clock signal CLK. At fixed times relative to the leading edges, commands are read by the control logic, addresses are decoded by an address decoder, signals are developed on input and output lines of the memory array, and data is made available for reading or writing at a data bus.
In synchronous read operations, an output of data on the data bus results from a read command and an address received at a preceding leading edge of the clock. The delay in number of clock cycles between the arrival of the read command at the control logic input and the availability of the corresponding data at the data bus is the "latency" of the SDRAM. If the output data is available by the second leading edge of the clock following the arrival of the read command, the device is described as a two-latency SDRAM. If the data is available at the third leading edge of the clock following the arrival of the read command, the device is a three-latency SDRAM.
In conventional SDRAMs, latency is only imposed for read operations. In write operations, write commands are supplied simultaneously with data at the data bus. The commands, addresses, and data are transferred to the memory array very quickly, typically within one clock cycle. Typical SDRAMs may thus be described as having no write latency.
FIG. 1 is a block diagram of a conventional synchronous dynamic random access memory 40 ("SDRAM"). The SDRAM 40 has as its central memory element a memory array 42 that is segmented into two banks 44, 46. The SDRAM 40 operates under control of a logic controller 48 that receives a system clock signal CLK, a clock-enable signal CKE, and several command signals that control reading from and writing to the SDRAM 40. Among the command signals are a chip-select signal CS, a write-enable signal WE, a column address strobe signal CAS, and a row address strobe signal RAS. The overbars for the command signals CS, WE, CAS and RAS indicate that these signals are low-true signals, i.e., the command signals CS, WE, CAS and RAS go to a low logic level when true.
In addition to the command signals, the SDRAM 40 also receives addresses from the address bus 52 and receives or outputs data on a data bus 60. The received addresses may be row or column addresses. In either case, addresses from the address bus 52 are clocked in the SDRAM 40 through an address register or address latch 62. If an address is a row address, the address is transmitted to the array 42 through a row address path 64. The row address path 64 includes a row address multiplexer 66 that receives the external row address from the address latch 62 and receives an internal row address from a refresh circuit 67. The row address multiplexer 66 provides the row addresses to either of two row address latches 70 depending upon the logic state of the bank address BA. The row address latches 70 latch the row addresses and provide the row addresses to respective row decoders 72. The row decoders 72 take the 11-bit address from the row address latch 70 and activate a selected one of 2,048 row address lines 73. The row address lines 73 are conventional lines for selecting row addresses of locations in the memory array 42. As noted above, the following discussion assumes that the row address has been selected and that the selected row is activated.
If the address received at the address latch 62 is a column address, it is transmitted to the I/O interface 54 and the memory array 42 through a column address path 76. The column address path includes a column address counter/latch 78 that receives or increments, and holds the column address from the address latch 62, a multiplexer 79 that receives a column address from either address latch 62 or from counter/latch 78, a pre-decoder 102 and a latch 82. Depending on whether a particular column access is the result of a new command, or if it is a subsequent access in a burst initiated by a previous command, the multiplexer 79 transmits the appropriate column address to the column decoder 84, via the column address pre-decoder 102 and latch 82. For new commands, the multiplexer 79 routes the external address (from the address latch 62) through to the pre-decoder 102 and latch 82. A copy is also captured by the column address counter/latch 78 for incrementing on subsequent accesses. If the device 40 has been programmed for a burst length of 2 or greater, and a new column command is not presented to interrupt a column command issued on the previous clock edge, then the counter/latch 78 will increment (or sequence) to the next column address in the burst, and the multiplexer 79 will route the incremented address to the pre-decoder 102 and latch 82.
The input data path 56 transmits data from the data bus 60 to the I/O interface 54. The output data path 58 transmits data from the I/O interface 54 to the data bus 60. Operation of the column address path 76, input data path 56, and output data path 58 for a selected sequence of read and write commands will be described below with respect to the timing diagram of FIG. 4. The logic controller 48 decodes the command signals according to a predetermined protocol to identify read, write, and other commands for execution by the SDRAM 40. FIGS. 2 and 3 show clock and command signals and their states for write commands and read commands, respectively. The read and write commands differ only in the state of the write-enable signal WE. Except for the write-enable signal WE, the following discussion applies equally to FIGS. 2 and 3.
As indicated by the arrow 50, the leading edge of each pulse of the clock signal CLK establishes the time at which the states of the signals are determined. The clocking of the logic controller 48 by the clock signal CLK is enabled by the clock-enable signal CKE, which is high for reading and writing. Also, reading and writing from the SDRAM 40 is enabled only when the SDRAM 40 is selected, as indicated by the chip-select signal CS.
The next two command signals are the row and column address strobe signals RAS and CAS. When true (low), the row address strobe signal RAS indicates addresses on an address bus 52 are valid row addresses. A true (low) column address strobe signal CAS indicates that addresses on the address bus 52 are valid column addresses. During reading or writing, the column address strobe signal CAS is low (true) indicating that the address bits from the address bus 52 represent the column address, as represented for address signals A0-A10. The row address strobe signal RAS is high (not true) because the row address was determined at a different leading clock edge. As is conventional to SDRAM operation, the row address is received and stored and the selected row is activated prior to the column address strobe signal CAS going true (low). The following discussion assumes that the selected row has already been activated.
The write-enable signal WE becomes active at the same time that the column-address strobe signal CAS becomes active. The write-enable signal WE is also a low-true signal such that, if the write-enable signal WE is low, the data transfer operation will be a write, as shown in FIG. 2. If the write-enable signal WE is high, the data transfer operation will be a read, as shown in FIG. 3.
The logic controller 48 decodes the above-described command signals CKE, CLK, CS, WE, CAS, and RAS to determine whether a read or write command has been received. In response to the determined command, the logic controller 48 controls reading from or writing to the memory array 42 by controlling an I/O interface 54 and input and output data paths 56, 58. The I/O interface 54 is any conventional I/O interface known in the art, and includes typical I/O interface elements, such as sense amplifiers, mask logic, precharge and equilibration circuitry, and input and output gating.
The following discussion of FIG. 4 assumes that the row address has already been decoded and the appropriate row of the memory array 42 has been activated in response to the row address. As shown in FIG. 4, a first read command READ1 is applied to the logic controller 48 at a leading edge of a first clock pulse at time t0. At substantially the same time, a first read column address RCOL1 is applied to the address bus 52. Over the next two periods of the clock signal CLK, the first read column address RCOL1 travels along the column address path 76 through the address latch 62, the multiplexer 79, the column address predecoder 102 and latch 82 to the column decoder 84 where it is decoded. The decoded read column address RCOL1 reaches the I/O interface 54 by time t2, at the second leading edge following the time t0.
Upon the decoded column address RCOL1 reaching the array 42, the I/O interface 54 reads data DOUT1 stored in the memory location at the decoded column address RCOL1 and provides the data DOUT1 to the output data path 58. The data DOUT1 travel through the output data path 58 and reaches the data bus 60 at time t3, which is three leading edges of the clock signal CLK after the first read command READ1 was received at time t0. The SDRAM 40 is thus a three-latency device because the data DOUT1 are available at the data bus 60 three leading edges of the clock signal CLK after the read command READ1 arrives at time t0.
A subsequent read command READ2 and a second column address RCOL2 arrive at time t1, which is the leading edge of the clock signal CLK immediately after the first leading clock edge at time t0. The above-described reading operations occur in response to the second read command READ2 and the second column address RCOL2, with each step shifted to the right by one period of the clock signal CLK relative to the operations of the first read command RCOL1. The data DOUT2 from the second memory location indicated by the column address RCOL2 are applied to the data bus 60 at time t4.
At time t2, a third read command READ3 and third column address RCOL2 are applied to the logic controller 48 and address bus 52, respectively. Once again, the read operations are repeated, one clock period after those of the second read operation. Thus, the data DOUT3 for the third read command READ3 are applied to the output data bus 60 at time t5.
While read operations are performed according to the read latency of the SDRAM 40, there is typically no write latency in the DRAM 40. However, the read latency of the SDRAM 40 can delay the completion of write operations that follow a read operation. FIG. 4 shows an example of an attempt to write data at time t3 immediately following the third read command READ3 at time t2. The write command WRITE1, the column address WCOL1, and the input data DIN1 are all applied to the logic controller 48, the address bus 52, and the data bus 60, respectively, at time t3. The decoded column address WCOL1 and input data DIN1 arrive at the array 42 approximately one clock cycle later. In the example of FIG. 4, the address WCOL1 and data DIN1 take approximately one clock cycle to traverse the column address path 76 and the input data path 56, respectively. However, in some SDRAMs, the data DIN1 and the decoded column address WCOL1 may arrive at the array 42 more quickly or more slowly.
One problem with the above-described timing structure is that at time t3, the input data DIN1 from the first write command WRITE1 and the output data DOUT1 from the first read command READ1 would collide at the data bus 60.
A second data collision occurs when a second write command WRITE2 immediately follows the first write command WRITE1. More specifically, at time t4, input data DIN2 for the second write command WRITE2 reaches the data bus 60 at the same time that output data DOUT2 from the second read command READ2 reach the data bus 60. A third data collision occurs when a third write command WRITE3 immediately follows the second write command WRITE2. This occurs at time t5 when input data DIN3 from the third write command WRITE3 and output data DOUT3 reach the data bus 60 simultaneously.
To prevent such data collisions, most SDRAMs require that write commands be delayed with respect to the read commands so that write commands are not permitted for one or more clock cycles after read commands. Typically, this is achieved by inserting no operation commands NO-OP between read and write commands. While this approach can prevent such collisions, the no operation commands NO-OP lower the effective speed of such SDRAMs because they impose delays in accepting write commands at the SDRAM. Note that this problem does not occur for read commands following write commands since the write command can be processed during the read latency period.
Another approach to preventing such data collisions might be to impose write latencies that equal the read latencies. As used herein, a "write latency" refers to the number of clock cycles between a write command and arrival of data on the data bus 60. Such an approach inherently avoids collisions of data and addresses on a computer's data bus and address bus because data and addresses will follow read and write commands by equal numbers of clock cycles. Thus, as long as the commands are not issued simultaneously, data and addresses will not collide on the data and address busses. One example of such an approach is found in U.S. Pat. No. 5,511,024 to Ware et al.
Unfortunately, this approach does not necessarily overcome the problems of data collisions and address collisions at the memory array 42, as can be seen in FIG. 5. As shown at time t3, a first write command WRITE1 and a first write column address WCOL1 are applied to the SDRAM 40. At time t4 a second write command WRITE2 and second write column address WCOL2 are applied. Input data DIN2 corresponding to the second write command WRITE2 are present on the data bus (DQ) at time t7, assuming a write latency of three. One leading edge later, at time t8, the input data DIN2 and the decoded second column address WCOL2 reach the array 42, assuming the second write address WCOL1 is internally delayed (buffered) and applied to the array 42 at the appropriate time.
At time t6, a fourth read command READ4 and fourth read address RCOL4 are applied to the logic controller 48 and the address bus 52, respectively. The decoded column address RCOL4 reaches the array at time t8 and the data DOUT4 is read from the array at time t8. However, as can be seen in FIG. 5, the decoded column addresses WCOL2 and RCOL4 both reach the array 42 at time t8. Also, the input data DIN2 and output data DOUT4 are being written to and read from the array 42 at time t8. Thus, reading and writing with the same latency might still result in data and address collisions at the array 42. One approach to overcoming this limitation could be to limit reads and writes to separate DRAMs or to separate independent arrays of a multi-array device. This approach still precludes sequential reads and writes at matching latencies within a single memory array. Also, a multi-bank memory array approach would require multiple independent memory arrays and associated column amplifiers to interleave reads from one bank with writes to another bank.